1. The Field of the Invention
The present invention relates to semiconductor devices and methods for their construction. More particularly, the present invention relates to capacitor design, transistor design and cell isolation methods used to reduce the surface area occupied by a DRAM cell. More specifically, the present invention merges capacitor design, transistor design and cell isolation methods by using existing isolation trench sidewalls to form a DRAM capacitor and a access transistor thus significantly increasing DRAM cell density over currently fabricated DRAM cells.
2. Background Art
Various DRAM capacitor designs have been employed to reduce the surface area occupied by a single DRAM cell. Early DRAM designs employed flat horizontal capacitor plates. Later designs, intended to conserve chip surface area, employed trenches or fin structures to form narrow dimension capacitors with some vertical contribution to the capacitor plate surface area.
In addition to the shape and size of the capacitor plates, the type of cell isolation contributes to the overall DRAM cell size. Traditionally, field oxide produced by the Local Oxidation of Silicon process (LOCOS) was used as cell isolation. Unfortunately, a field oxide must cover a fairly wide area in order to effectively isolate adjacent cells. Further, it is difficult to control the growth of field oxide. Therefore, field oxide often occupies a significant amount of the chip surface area.
More recently, trench isolation has been employed. This involves etching a narrow isolation trench around the active areas (cells) on the chip. The isolation trenches are then filled with oxide or other dielectric to effectively isolate adjacent active areas from one another. While trench isolation requires more process steps than LOCOS isolation (field oxide), trench isolation can be made much narrower than LOCOS isolation. Therefore, DRAMs employing trench isolation can be packed more densely than DRAMs employing LOCOS isolation.
In addition to isolation regions and capacitors, access transistors can also occupy a significant amount of wafer surface which limits the DRAM cell density. Typically, the gate structure and the source region of the access transistor are formed on the semiconductor substrate surface. Forming a portion of the access transistor directly above the isolation trench would significantly reduce the area of semiconductor substrate required for a DRAM cell.
In the continuing quest for higher density DRAMs, improved structures employing narrow dimension trench isolation and access transistors are still needed.
The present invention addresses this need by providing a DRAM cell where existing isolation trench sidewalls are used to form a DRAM capacitor and a portion of the access transistor is provided directly over the isolation trench sidewalls. Preferably, the access transistor is oriented vertically with respect to the plane of the integrated circuit. By integrating both the DRAM capacitor and access transistor formation with the DRAM cell isolation, the present invention may significantly increase DRAM cell density over currently fabricated DRAM cells.
In one aspect, the instant invention provides a DRAM cell including a vertically oriented pass (or access) transistor electrically coupled with a capacitor formed in an isolation trench on an active region of a semiconductor substrate. The isolation trench electrically isolates the DRAM cell from one or more adjacent DRAM cells.
The capacitor includes a first capacitor plate, a dielectric layer and a second capacitor plate. In a preferred embodiment, the first capacitor plate is defined by the semiconductor substrate at the wall of the isolation trench and has a substantially greater dopant concentration than immediately adjacent semiconductor substrate. The second capacitor plate is preferably defined by a conductive layer inside the isolation trench. The second capacitor plate occupies a portion of the isolation trench proximate to the access transistor. The conductive layer that may comprise the second capacitor plate is preferably doped polysilicon. It may be between about 200 xc3x85 and about 2000 xc3x85 thick.
The capacitor dielectric layer may be made from any suitable material that can be formed in the necessary size and shape. Suitable dielectric materials include at least one of SiO2, Si3Nx, silicon oxynitride, ONO (SiO2/Si3Nx/SiO2 layered material), tantalum pentaoxide (Ta2O5), barium strontium titanate BaSrTiO3 (xe2x80x9cBSTxe2x80x9d) and piezoelectric lead zirconate titanate (xe2x80x9cPZTxe2x80x9d). Preferably, the dielectric layer comprises a material with a high dielectric constant (e.g., at least about 10) such as BST, PZT, or Ta2O5. In one specific embodiment, the dielectric layer is Ta2O5 and is between about 20 and about 200 xc3x85 thick depending on the capacitor plate area.
The access transistor is preferably an MOS device that may have a drain electrically connected to the second capacitor plate and electrically isolated from the first capacitor plate. Preferably, the gate structure of the access transistor is provided over the capacitor in the trench isolation sidewalls and is vertically oriented with respect to the surface of the semiconductor substrate.
In the case of an MOS access transistor, the access transistor includes a semiconductor bulk section, a gate dielectric provided on a vertical sidewall of the semiconductor bulk region, a gate electrode formed on the gate dielectric, and a source region. The bulk semiconductor section is typically provided by a layer of epitaxial silicon which is deposited over the semiconductor substrate at locations outside the trench isolation. Silicide layers may optionally be provided on the gate electrode and source region. The electrical connection between the second capacitor plate and the drain of the access transistor is preferably provided as a high dopant concentration region in the semiconductor substrate and the epitaxial silicon layer.
In one embodiment, the isolation trench has a depth of at least about 0.3 xcexcm. In another embodiment, the isolation trench has a width of at most about 0.5 xcexcm. Preferably, the isolation trench is at least partially filled with a first dielectric material (e.g., silicon oxide). Typically, a second isolation dielectric (also silicon oxide in many cases) is provided over the first isolation dielectric material. In a specific embodiment, the gate structure of the access transistor is oriented parallel to the vertical sidewalls of the isolation trench and perpendicular to the semiconductor substrate.
In another aspect, the invention provides a method for forming a capacitor in an isolation trench and at least a portion of a vertically oriented access transistor in the area above the isolation trench in a integrated circuit. The process is characterized by forming an isolation trench about an active region in a semiconductor substrate, forming a capacitor in the isolation trench, filling the trench with a first isolation dielectric and forming at least a portion of the access transistor in the area above the isolation trench.
In one embodiment, the isolation trench includes both a capacitor dielectric and an isolation trench dielectric which occupy different areas of the isolation trench. This does not preclude embodiments where the isolation dielectric and the capacitor dielectric are made from the same material although one will generally want an isolation dielectric with a relatively low dielectric constant and a capacitor dielectric with a relatively high dielectric constant.
The capacitor may be formed by a process that may be characterized as having the following sequence: (a) forming a first capacitor plate in the semiconductor substrate immediately adjacent the sidewalls of the isolation trench; (b) forming a capacitor dielectric layer on part of the sidewalls of the isolation trench; and (c) forming a second capacitor plate on a part of the capacitor dielectric.
The first capacitor plate may be formed by a process where a dopant source material is provided on a portion of the isolation trench sidewalls. This material furnishes dopant atoms which are driven into the adjacent semiconductor substrate. The dopant source material may be conformally deposited on the trench sidewalls and then selectively removed from the top portion of the isolation trench. The location of the remaining dopant source material defines the location of the first capacitor plate.
The dopant source material may be removed from the top of the vertical sidewalls of the isolation trench by a process that may be characterized as having the following sequence: (a) depositing photoresist in the isolation trench; (b) exposing the photoresist to a specific depth in the isolation trench; (c) developing the photoresist (to remove the exposed upper part of the photoresist); and (d) removing the dopant source material from the top portion of the vertical sidewalls of the isolation trench. The process may subsequently strip or otherwise remove the photoresist from the isolation trench. Then an oxide may be deposited to cap the dopant source material and prevent diffusion at the top portion of the trench. Ultimately, the device is annealed to drive dopant from the source material into the adjacent substrate, thereby forming the first capacitor plate. Thereafter, the source material is removed from the trench.
The capacitor dielectric may be provided by a process similar to that used to provide the dopant source material. Specifically, the capacitor dielectric may be conformally deposited and then selectively removed from the top portion of the vertical sidewalls of the isolation trench.
The second capacitor plate may be provided by a process including the following sequence: (a) conformally depositing a conducting layer such as polysilicon or titanium nitride (or platinum in the case of BST dielectric) in a portion of the isolation trench; (b) an anisotropic etch that preferentially removes polysilicon from the bottom surface of the isolation trench while retaining polysilicon at the vertical sidewall of the isolation trench to form the second capacitor plate.
The access transistor may be provided by a process including the following sequence: (a) forming a gate dielectric layer; (b) forming a gate electrode over the gate dielectric layer; (c) forming a bulk semiconductor section having a vertical surface contacting the gate dielectric layer; and (d) forming a source region in the bulk semiconductor section.
The gate dielectric layer may be formed by a process including: (a) blanket depositing a support layer (preferably, though not necessarily, silicon oxide); (b) patterning the support layer to provide the support layer over the active region of the semiconductor substrate; and (c) blanket depositing a gate dielectric so that it is provided on vertical sidewalls of the support layer that are substantially parallel and adjacent to the vertical sidewalls of the isolation trench.
The support layer should be made from a material that can serve as a temporally support. Thus, it should be made from a material that can be subsequently etched away after its support function is complete. Silicon oxide is one suitable support material (it can be removed by a hydrofluoric acid wet etch). An example of another suitable support material is spin on glass (SOG). Preferably, the support layer is between about 0.05 micrometer and about 2 micrometers thick to provide support for a gate dielectric of length adequate for the access transistor. The gate dielectric may be made from oxynitride, nitride or other material resistant to etch conditions employed to etch oxide. Nitride is a preferred material when the support is made from oxide because nitride has a relatively low dielectric constant and resists etch with hydrofluoric acid. The gate dielectric layer is preferably between about 25 angstroms and about 150angstroms thick.
The gate electrode may be formed by a process including: (a) depositing a polysilicon layer over the gate dielectric; (b) patterning the polysilicon layer to form the gate electrode.
The bulk semiconductor section may be formed by a process characterized by the following sequence: (a) filling the area above the isolation trench and adjacent to the support layer with a second support layer; (b) removing the support layer; and (c) growing an epitaxial silicon layer over the semiconductor substrate to form the bulk semiconductor section. The second support layer should resist the etching conditions employed to remove the original support layer. Thus, if the original support layer is made from oxide, the second support layer is preferably made from nitride or oxynitride. Preferably, the epitaxial silicon layer is grown to a thickness of between about 500 angstroms and about 2 micrometers.
These and other features and advantages of the present invention will be further described in the following detailed description of the invention with reference to the associated drawings.